1. Field of the Invention
The present invention generally relates to the production of electrical circuits, such as integrated circuits, using block compiler systems and, more particularly, block compiler systems that quickly and accurately estimate the speed of critical paths through a compiled circuit block.
2. Related Art
It is well-known to use computerized block compiler systems for synthesizing compiled circuit blocks as part of electrical circuits, such as application-specific integrated circuits (ASICs). To generate a simulation timing model for a compiled circuit block, a typical block compiler system connects models of physical tiles which constitute basic primitive components of the block structure.
A block compiler system that provides particular flexibility in creating a compiled circuit block is described in co-pending U.S. patent application Ser. No. 07/626,078, filed Dec. 10, 1990, the entire disclosure of which is incorporated herein by reference. The block compiler system described in that application has the advantage that it allows users to specify the logical size of an ASIC memory. Further, the block compiler system selects an optimum structure for the specified memory size according to higher-level predetermined criteria such as, for instance, minimum physical area (i.e., total number of gate sites covered by the memory), most square physical aspect ratio, and minimum access time of the overall compiled memory.
In operation, the block compiler system described in application Ser. No. 07/626,078 iteratively considers each possible memory structure for the specified memory size. The block compiler system performs the iterations by, for example, sequentially varying the partitioning of address lines between column address lines and row address lines. (This can be done by incrementing the number of column address lines from zero to the total number of address lines necessary for the specified size.)
In addition to the functional capabilities of block compiler systems described in application Ser. No. 07/626,078, however, it is important for block compiler systems to provide the capability of quickly and accurately predicting the speed of compiled circuit blocks. In practice, the speed of a compiled circuit block usually is measured by pin-to-pin timing from a block input to a block output. Conventionally, compiled circuit block speed is determined by lengthy circuit simulations performed in advance using physical blocks that have actually been built, by interpolation from tables based on specific configurations, by mathematical modelling (including behavioral modelling) of compiled circuit blocks or a combination of these. These procedures are either time-consuming or inaccurate and often entail lengthy re-simulations or re-calculations when the design of a compiled circuit block is changed.